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|*     Copyright (c) 1993-2000  NVIDIA, Corp.    NVIDIA  design  patents     *|
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 \***************************************************************************/

/************************** HAL/RM Interfaces ******************************\
*                                                                           *
* Module: halrm.c                                                           *
*   The Resource Manager service routines for the HAL are in this module.   *
*                                                                           *
*****************************************************************************
*                                                                           *
* History:                                                                  *
*                                                                           *
\***************************************************************************/

//
// halrm.c
//
// RM service entry points needed by HAL.
//

#include <nv_ref.h>
#include <nvrm.h>
#include <nvhal.h>
#include "nvhw.h"
#include <i2c.h>


//
// nvHalRmPrintString
//
//
VOID nvHalRmPrintString(VOID *pDeviceId, U032 debugLevel, char* str)
{
   	PHWINFO pDev = (PHWINFO)pDeviceId;
	DBG_PRINT_STRING(debugLevel, str);
}

//
// nvHalRmPrintValue
//
//
VOID nvHalRmPrintValue(VOID *pDeviceId, U032 debugLevel, U032 value)
{
   	PHWINFO pDev = (PHWINFO)pDeviceId;
  	DBG_PRINT_VALUE(debugLevel, value);
}

//
// nvHalRmPrintStringValue
//
//
VOID nvHalRmPrintStringValue(VOID *pDeviceId, U032 debugLevel, char* str, U032 value)
{
  	PHWINFO pDev = (PHWINFO)pDeviceId;
    DBG_PRINT_STRING_VALUE(debugLevel, str, value);
}

//
// nvHalRmPrintStringPtr
//
//
VOID nvHalRmPrintStringPtr(VOID *pDeviceId, U032 debugLevel, char* str, VOID* value)
{
   	PHWINFO pDev = (PHWINFO)pDeviceId;
	DBG_PRINT_STRING_PTR(debugLevel, str, value);
}

//
// nvHalRmPrintStringVal64
//
//
VOID nvHalRmPrintStringVal64(VOID *pDeviceId, U032 debugLevel, char* str, U064 value)
{
   	PHWINFO pDev = (PHWINFO)pDeviceId;
    DBG_PRINT_STRING_VAL64(debugLevel, str, value);
}

//
// nvHalRmRegWr08
//
//
VOID nvHalRmRegWr08(VOID *pDeviceId, U032 offset, U008 value)
{
	PHWINFO pDev = (PHWINFO)pDeviceId;
	REG_WR08(offset, value);
}

//
// nvHalRmRegRd08
//
//
U008 nvHalRmRegRd08(VOID *pDeviceId, U032 offset)
{
	PHWINFO pDev = (PHWINFO)pDeviceId;
	return (REG_RD08(offset));
}

//
// nvHalRmRegWr32
//
//
VOID nvHalRmRegWr32(VOID *pDeviceId, U032 offset, U032 value)
{
	PHWINFO pDev = (PHWINFO)pDeviceId;
	REG_WR32(offset, value);
}

//
// nvHalRmRegRd32
//
//
U032 nvHalRmRegRd32(VOID *pDeviceId, U032 offset)
{
	PHWINFO pDev = (PHWINFO)pDeviceId;
	return (REG_RD32(offset));
}

//
// nvHalRmBreakPoint
//
//
VOID nvHalRmBreakPoint(VOID *pDeviceId)
{
   	PHWINFO pDev = (PHWINFO)pDeviceId;
	DBG_BREAKPOINT();
}

//
// nvHalRmDelay
//
//
RM_STATUS nvHalRmDelay(VOID *pDeviceId, U032 milliSeconds)
{
    PHWINFO pDev = (PHWINFO)pDeviceId;
	return (osDelay(milliSeconds));
}

//
// nvHalRmServiceIntr
//
// Service a pending condition on the specified engine on the
// specified device.
//
RM_STATUS
nvHalRmServiceIntr(VOID *pDeviceId, U032 engineTag)
{
    PHWINFO pDev = (PHWINFO)pDeviceId;

    switch (engineTag)
    {
        case MC_ENGINE_TAG:
            (void) mcService(pDev);
            break;
        case GR_ENGINE_TAG:
            (void) grService(pDev);
            break;
        case FIFO_ENGINE_TAG:
            (void) fifoService(pDev);
            break;
        case DAC_ENGINE_TAG:
            (void) VBlank(pDev);
            break;
        default:
            break;
    };
    return (RM_OK);
}

//
// nvHalRmI2cRead
//
// Issue i2c bus read request on behalf of the HAL.
//
RM_STATUS nvHalRmI2cRead(VOID *pDeviceId, U032 portID, U008 ChipAdr, U016 AdrLen, U008 *Adr, U016 DataLen, U008 *Data)
{
    PHWINFO pDev = (PHWINFO)pDeviceId;
    U032    Head =0; // for now, always use head 0
    return (i2cRead(pDev, Head, portID, ChipAdr, AdrLen, Adr, DataLen, Data));
}

//
// nvHalRmI2cWrite
//
// Issue i2c bus write request on behalf of the HAL.
//
RM_STATUS nvHalRmI2cWrite(VOID *pDeviceId, U032 portID, U008 ChipAdr, U016 AdrLen, U008 *Adr, U016 DataLen, U008 *Data)
{
    PHWINFO pDev = (PHWINFO)pDeviceId;
    U032    Head =0; // for now, always use head 0

    return (i2cWrite(pDev, Head, portID, ChipAdr, AdrLen, Adr, DataLen, Data));
}

//
// RM/HAL services table.
//
HALRMFUNCS_000 HalRmFuncs_000 =
{
    // interrupt service entry point
    nvHalRmServiceIntr,

    // debug print routines
    nvHalRmPrintString,
    nvHalRmPrintValue,
    nvHalRmPrintStringValue,
    nvHalRmPrintStringPtr,
    nvHalRmPrintStringVal64,

    // register io entry points
    nvHalRmRegWr08,
    nvHalRmRegRd08,

    nvHalRmRegWr32,
    nvHalRmRegRd32,

    nvHalRmBreakPoint,
    nvHalRmDelay,

    nvHalRmI2cRead,
    nvHalRmI2cWrite,
};
